The present invention relates to a data processor for accessing data stored in a memory, and more particularly, to a data processor capable of accessing the data with the data processing capacity of a central processing unit (hereinafter, referred to as "CPU") even if the data processing capacity of the central processing unit within the data processor is larger than the data output capacity of the memory.
Generally, a well known data processor applies address signals to address terminals of a memory device via an address bus in order to access data stored in the memory, such as a conventional semiconductor memory, in accordance with a program previously stored in a non-volatile memory such as a read only memory (ROM). The data processor then reads the data outputted from the memory via a data bus corresponding to the address signals. Such a data processor has been used in almost all industrial fields for processing data, for example, a printer is an example of office automation machinery which includes a data processor in order to print data received from an information processing apparatus, such as a host computer, in the form of characters. In a printer, the data processor as a printing control unit has a central processing unit operated according to a program stored in a program read only memory. A font read only memory stores character pattern data in a storage area and a random access memory is used as a working memory when the central processing unit forms the print data.
At the present time, the current generation of central processing units have a thirty-two bit capacity to process data at a high speed, while the memory for storing data of various forms has been limited to sixteen bits, particularly with older peripheral devices such as printers, resulting in problems of circuit design when endeavoring to permit central processing units to accommodate the limited access capacity of such memories. Moreover, such a capacity difference brings about the problem of limitation in high speed processing of data, and therefore, the central processing unit must respectively execute addressing operations of two times in order to access the data stored in memory. Furthermore, with such a mismatch between thirty-two bit central processing units and sixteen bit memories, one technique requires that half of the data read from the memory after an addressing operation should be masked in a program since the actual data outputted from the memory is 16 bits though the data applied via the data bus is thirty-two bit. In the above mentioned printer, if the central processing unit has a thirty-two bit processing capacity and the font read only memory has sixteen bit output capacity, a problem arises in that in order to access thirty-two bits of data the central processing unit should perform address operations of two times and masking operations of two times.
As a result, the data processing operation can not be sufficiently implemented in a data processor having a central processing unit capable of processing a larger data capacity than the output data capacity of the memory. In a printer, such a data processor prevents printing speed improvement and causes an increased load on the central processing unit.
Various devices have been constructed in an attempt to increase addressable memory space so the addressing capacity of a central processing unit can be fully realized. These attempts have been unsuccessful however, and the devices contain inherent deficiencies.
The Memory Addressing Scheme of Sinofsky et al., U.S. Pat. No. 5,235,551, purports to increase addressable memory space. Individual character data is placed into one of a series of "memory planes" according to starting addresses. Each "memory plane" contains the maximum number of addresses that can be addressed by available address lines. The starting address of the data to be accessed determines the appropriate "memory plane" which must be addressed. In the preferred embodiment, the least significant nibble of each starting address is used to separate data into each "memory plane". The device utilizes a comparator to identify the current starting address of a piece of data to be accessed. Once the comparator has identified the starting address of the piece of data, a selection logic block "searches" for and selects the appropriate "memory plane" and maintains access to the data in that plane until another starting address is received and detected by the comparator. Once the comparator detects another starting address, the "searching" process repeats itself. An inherent disadvantage exists in a device which separates data into "memory planes" according to starting addresses, data can not be readily accessed. Each "memory plane" must be searched during the addressing function for the starting address of each piece of data at the outset of the addressing function and at each subsequent time the starting address of a piece of data can not be found in the "memory plane" being accessed.
In an earlier scheme, the Variable Capacity Data Buffer System of C. A. Heath, U.S. Pat. No. 4,258,418 uses a variable capacity data buffer system. To address the problem of buffer filing delays an input/output device start stop delays are different input output device unit application. A data buffer is a storage device having maximum storage capacity value for controlling transfer data between the processor and an input out device is utilized. Data is input into the data buffer storage place until it is full. The data buffer storage device subsequently outputs data to an input output device while data is replenished into the data storage device. An inherent disadvantage, resulting from the lack of a scheme to increase addressing capacity, exists in the device. The device has an addressing capacity less than its process capacity, thus, printing speed is sacrificed.
Later, the Device For Increasing The Length Of A Logic Computer Address of Kaplinsky, U.S. Pat. No. 4,361,868, sought to provide a device for increasing the length of a logic computer address. A data processing machine was contemplated with a device to extend the length of the logic address so that different logic addresses can be formed and become available to the program, as utilized. In utilizing this device, the length of a logic computer address is increased through masking operations. An inherent disadvantage exists in a device which increases the length of a logic computer address through masking operations. Printing speed is affected by the masking operation.
In a conventional dot matrix printer the method and apparatus for printing various kinds of characters by extension of a limited capacity of the font read only memory, such as the Dot-Matrix Printer With Font Cartridge Unit of U.S. Pat. No. 4,660,998 to Yulcio Tsuneld, Hanno, et al. Moreover, U.S. Pat. No. 4,660,998 describes a technique for using a font cartridge apparatus connected to a connecter in order to solve the problem of limitation of memory capacity. Assuming that the CPU of the printer, as shown in the aforementioned U.S. Pat. No. 4,660,998, has a data processing bit number larger than the data output bit number of the font read only memory or of a font cartridge, the same problems as mentioned above may occur.